High-throughput LDPC Coder and Decoder FPGA Implementation

IEEE 802.11ad is an emerging 60 GHz wireless communication standard. The maximum transfer rate is 4.62 Gb/s, and the maximum processing rate is 1.76 GHz, when using single carrier modulation schemes. The standard use a quasi-cyclic LDPC code (QC-LDPC) in order to ensure a low error rate at a high transfer rate. For the standard, this paper designs high-throughput LDPC coder and decoder. Implementation of the encoder use shift-register as the basic unit. At the same time, compared to the different storage methods of generation matrix, paper optimizes the coding structure. Decoding algorithm select modified minimum sum algorithms. Decoder hardware architecture is compatible with four kinds of bit rates, and has three kinds of modulation method interface. In accordance with the design of the structure, paper implements LDPC coder and decoder with the Verilog hardware description language, and get the correct simulation results. It completes the comprehensive and analyses logic resource consumption on V7-485t FPGA. As a result, when the FPGA clock frequency is 200 MHz, the transmission rate is up to 1.68 Gb/s.