Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL

A high performance PLL (Phase Locked Loop) is designed and implemented in TSMC 90 nm CMOS Process. The noise and reference spur of the charge pump are analyzed in detail. The theoretical calculation of LC VCO (Voltage Controlled Oscillator) turning range is presented and its phase noise is discussed. The design methods of loop filter is studied. In order to optimize phase noise, the PLL is analyzed by MATLAB. The PLL proposed consumes 33 mW with a 1.2 V power supply and only occupies an area of 530 μm×720 μm. The measured results show that it exhibits an in-band phase noise of -110.6 dBc at 1MHz frequency offset and reference spur is -56.935 dBc.