Low Power Configurable ASIC Based Elliptic Curve Scalar Multiplication Over GF(2^m)

Aiming at the design requirements of high security, low power consumption, light implementation and configurable requirements for radio frequency identification (RFID) and wireless sensor networks (WSN) applications, an elliptic curve scalar multiplication circuit is designed. Through the overall optimization of the whole architecture of the elliptic curve scalar algorithm layer by layer, especially for the lower power design of the core scalar module: modular multiplication and inversion. Through the Xilinx FPGA tool simulation and the comprehensive verification of Design Compiler tools of Synopsys, the scalar multiplication architecture is proved flexible and expandable, one elliptic curve scalar point multiplication over GF(2¹⁶³) is only 138 k clock cycles and the equivalent gate area with TSMC 0.13 μm is only 11.9 k, compared with similar designs, the area and the implementation of the speed has a significant advantage, it can be used for RFID、WSN and other resource-constrained applications.