Parity Detection Algorithm and VLSI Implementation Based on the RNS

A parity checker based on triple-mode2ⁿ+1,2ⁿ-1,2²ⁿ+1is proposed in this paper,this checker only need a n bit adder,a n+1 bit CSA adder,a 2n bit comparator and some simple combination unit,it lowers the resource consumption and simplifies the design effectively.When n=30,an area of only 6130.958μm²,the delay is only 0.67ns.