XIE Jing, ZHANG Yu, WANG Qin, MAO Zhi-gang. The Design of Reconfigurable Cache Scheme in Multi-core Processor[J]. Microelectronics & Computer, 2016, 33(12): 1-5.
Citation: XIE Jing, ZHANG Yu, WANG Qin, MAO Zhi-gang. The Design of Reconfigurable Cache Scheme in Multi-core Processor[J]. Microelectronics & Computer, 2016, 33(12): 1-5.

The Design of Reconfigurable Cache Scheme in Multi-core Processor

  • To deal with massive and parallel data processing, the paper proposed a design solution of reconfigurable cache for multi-core processor.The work included the design of reconfigurable cache structure and its operation scheme, as well as a reconfiguration context word generation method, named as Dynamic Cache Associativity Configuration(DCAC)method.The experiments verified that with 4.07% overhead in hardware cost, the design solution won a 16.13% reduction of miss penalty in average for the core nearby caches with dynamic cache associativity reconfiguration method.
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