Design of a high-performance fast-SSC decoder for polar codes

In order to further reduce the decoding delay and hardware resource consumption of the Fast-SSC decoder of channel-coded polarized code in wireless communication system, this paper proposes two optimization methods for the Fast-SSC decoding algorithms, and realizes the fast-SSC decoder optimized with code length N=1 024 based on FPGA hardware. Based on the four special nodes Rate0, Rate1, Rep, and SPC in the fast-SSC decoding tree, the expansion of combined special nodes based on the Rate0 node and the Rep node respectively is proposed, which makes the special nodes in the decoder tree increase from the original four to more than ten, further speeding up the speed of searching decoder tree. A method of multiplexing memory resources is proposed in which nodes with the same decoding tree depth use the same storage space. The comprehensive results show that the maximum operating frequency is 169 MHz, the decoding delay is 1.71 μs, the data throughput is 599 Mbps, and the memory consumes 14.8 Kbit, which effectively improves the overall performance of the Fast-SSC decoder.