Design of a Pipelined SAR ADC Used in CMOS Image Sensor

This paper presents a novel architecture to achieve a 10 bit pipeline ADC based on SAR technique which is used in a CMOS image sensor. A theoretical analysis is proposed to determine the high resolution MDAC and the suitable value of unit capacitor. The high-resolution first stage, the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. To satisfy the strict area requirement of CMOS image sensor, the layout is carefully designed. This pipelined SAR ADC is designed and fabricated in SMIC 180 nm CMOS technology. Simulation results show the ADC achieves 60.37 dB signal to noise distortion ratio (SNDR) and 76.37 dB spurious free dynamic range(SFDR). The effective number of bits (ENOB) achieves 9.74 bit. The core area is 140 μm×280 μm, about 0.04 mm². The power dissipation is 9.8 mW in typical case under 2.8 V supply.