A Multiphase Clock Generation for UWB Transceiver

A multiphase baseband clock generation for UWB transceiver is presented. By combining the similarity of PLL and DLL's structure, a reconfigurable fully-matched VCO/VCDL with dual mode is proposed. The clock generation system with the proposed VCO/VCDL can work in PLL/DLL mode separately, and provide 10 phase baseband clock signals which is 2 GHz. The chip is fabricated in TSMC 65 nm CMOS process, and the active area is only 0.03 mm². The testing results show that the output phase noise is -85.04 dBc/Hz@1 MHz and the reference spur is -46.89 dBc in PLL mode. The power consumption of the clock generation is about 2.1 mW under the 1 V supply.