Integrated Circuit Interconnect Wire Temperature Distribution Model Considering Buffer Heat Transfer and Buffer Location Optimization Analysis under Nanometer Process Condition

This paper analyzes the impact of temperature on the interconnect buffer insertion,and proposes an interconnect temperature distribution new model considering the dielectrics,vias,and buffers heat transfer effect. Single and multi-layer interconnect temperature distributions are calculated using 45 nm process parameters based on the new model.The results show that the local interconnect line temperatures are affected a little by buffer heat transfer,while the global interconnect lines are subject to significantly affected and lower 10 degrees Celsius than the dielectric heat transfer model.Moreover,the temperature has a significant effect on buffer insertion locations. Considering the substrate temperature gradient distribution, the location changes more than 10% compared to uniform buffer insertion under 1.5 mm interconnect wire length.