High-Speed 54 × 54-b Redundant Binary Multiplier Design

Redundant binary representation is one of the signed-digit number systems.High modularity and the carry-free feature of RB arithmetic can be used to design high-speed parallel multipliers.In this paper,the algorithm and structure of RB multiplier is systematically studied.The 54-bit RB multiplier is designed by the modified Booth algorithm,RB partial product accumulator and RB-NB converter.The hybrid parallel-prefix/carry-select adder is used to design optimized RB-NB converter.The multiplier has been realized by Verilog HDL and simulated in the ModelSim platform.Under SMIC 0.18 mm standard process library,the synthesis results of this design by Design Compiler show that the delay can be reduced to 3.97 ns and the area is 409 293 mm².