DU Li-na, HAN Jun-gang, LI Mao-liang. Router Design for a ARM Parallel Processor[J]. Microelectronics & Computer, 2017, 34(2): 73-76, 82.
Citation: DU Li-na, HAN Jun-gang, LI Mao-liang. Router Design for a ARM Parallel Processor[J]. Microelectronics & Computer, 2017, 34(2): 73-76, 82.

Router Design for a ARM Parallel Processor

  • Routing communication structure designed in this paper's project involves calls ARM parallel array processors that use four routers to complete the communication between the 16-core processors. Therefore it makes the area reduced at a greater degree. The router uses the way of Noc (Network on Chip) communication that is based on the packet switching, it uses internal caching mechanism, classic XY router algorithms, dedicated arbitration policy and data multicast, and with low power of high-performance ARM processor, these mechanisms reduce the data propagation delay and power consumption at the same time. Makes the performance of communication between multi-core processors has been increased greatly. The result shows that the clock frequency of the router, which designs for the telecommunications in the array of ARM muti-core machine, is up to 406.009MHz and the router can better meet the performance requirements of the array of ARM muti-core machine.
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