The Independent Design of RISC Pipeline CPU

This paper based on FPGA platform, designing a 16 bit pipelined RISC CPU core. With reference to the MIPS instruction set, CPU completing the design of RISC instruction set, realizing five stage pipelined structure by analyzing instruction processing, combined with the "prediction" and data forwarding method to solve the related problems of pipeline. To support the CPU software architecture, we design a compiler for the instruction set. In the Modelsim platform running test program, the simulation results are givenout. By comparing the experiment results, the clock cycles required is greatly reduced.