A Test Pattern Selection Method for Static Burn-In of ICs

To accelerate the early mortality of integrated circuits during static burn-in process, a test pattern which can excite the maximum leakage power of CUTs is preferred. This paper proposes a method to select the target test pattern. The reduced candidate test patterns are generated with ATPG method by setting proper stuck-at faults in CUTs. An indicator is designed based on the fault related input states of gates, and it is used for target searching in the candidate test patterns. The method has less risk of errors because the indicator hold a good positive correlation with the leakage power of CUTs.