Diagonal-Based for TSV Fault Tolerance Design

Three dimensional integrated circuits, using through-silicon vias(TSVs) as the communication link between vertical chip, with the advantages of high density, high bandwidth and low power consumption. As the TSV during processing and using process may be failure, will lead to the entire three-dimensional chip failure. In order to improve the yield of 3D chips, the yield of TSV must be raised as much as possible. This paper presents a novel diagonal-based redundant TSV repair scheme and proposes a repair algorithm based on maximum flow algorithm to tolerance the faulty TSV with redundant TSVs in the diagonal to improve the yield of the entire three-dimensional chip. Experimental results show that the yield of the proposed repair strategy is 98.38% to 98.96% and the hardware overhead can be reduced by up to 70% compared to router-based technique.