The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design

In the 8bit 125MHz Sample/s folding and interpolating A/D converter chip design,one new method of folding wave's production is put forward,which economize the voltage assignment in low-voltage analog design.The wide-swing Cascode topology is used in the tail currents design,which makes the tail currents of differential pairs match better,so DNL and INL of A/D convert system is reduced.A trans-resistance amplifier is used in the output nodes of folding circuit,which increase the analog bandwidth.The CMFB topology makes the common-mode level of output voltage more stable,which decreases zero-crossing distortion.In this project,VDD is 2.5V.The whole A/D system is simulated and validated in Hspice,and the simulation environment is 0.25μm CMOS process of UMC.