Methodology and EDA tool for Designing FPGA Architecture

In order to solve FPGA architecture design tools' problems of low flexibility, fallibility, not highly automation, this paper puts forward an FPGA architecture design method and realize this method by an EDA tool VA. VA provides a graphical user interface (GUI) to edit FPGA architecture description file, then converts this high--level architecture description into a detailed and completely specified FPGA architecture. Through VA's GUI, FPGA routing architecture can be readiusted locally, which makes designing a heterogeneous FPGA routing architecture possible. VA integrates FPGA architecture design and evaluation functions together, provides full-- automatic architecture evaluation flow. Finally, an FPGA chip VS1000 is successfully designed by VA, the experiments results of design have proved the correctness and efficiency of VA.