Design and Implementation of a Router Supporting QoS for Networks-on-Chip

This paper design a router with 8 ports for NoC, which uses a simplified VOQ architecture with dual crossbar, support 4 IP cores, and has dynamic arbitration which is deterministic and fair.The router can support QoS, reduce packets' head-of-line (HoL) blocking and area of networks-on-chip effectively.Logical synthesis was performed with the Synopsys Design Compiler using the 0.13μm library, the results show that the standard cells area of the router with 8 ports is 0.62mm², and the performance corresponds to 500MHz.