A binary scaling recombination capacitor weighted SAR ADC

Based on TSMC 180nm CMOS process, a 12-bit 100KS/s low power successive approximation analog-to-digital converter (SAR ADC) was designed. In order to overcome the influence of comparator offset and reference voltage jitter on the performance of high accuracy SAR ADCs, the binary-scaling recombination capacitor weighting method was used to achieve capacitor weighting, which improved the performance of SAR ADCs. Compared to traditional redundant calibration techniques, the calibration was achieved without adding additional redundant capacitors and the swing of the input signal was guaranteed. In addition, using low energy switching method, dynamic comparators and dynamic SAR logic effectively reduced power consumption. The simulation results showed that the ADC achieve a ENOB of 11.79 bit and only consumed 0.95 μW at 100 KS/s sampling rate and 0.7 V supply voltage. And its' FOM value was only 2.68 fJ/conv.