The Design and Implementation of Global Controller in Reconfigurable Video Array Processor

A video codec scheme based on reconfigurable array processor has been proposed. The design method of global controller for algorithms switching and resources adjustment is mainly described. In this design, array processors and host interface has been connected through hierarchical programming network to realize the control and management of computed resources for the video array processors. The experimental results shows that this global controller support various of modes to load instructions and feedback the calculated data. The maximum operating frequency in the field programmable gate array (FPGA) can up to 539.96MHz and compared with the same type array structure, the execution cycle of global controller is reduced by 50%.