Design of a High-Speed and Self-Adaptive Hardware Architecture for Interpolation of AVS

To solve the problem that the interpolation of the AVS decoder have a high computational complexity, a high-speed and self-adaptive hardware architecture for Luma and Chroma interpolation is presented in this paper.Base on the symmetry characteristic in the algorithm of Luma interpolation, we propose a novel filter architecture, which can lessen the number of filters and registers of the hardware architecture.It also can save hardware resources by the extracting the multiplex arithmetic units of Chroma interpolation.This architecture, synthesized with SMIC 0.18 μm standard cell technology, is able to run up to 200 MHz and predict every macroblock within 512 cycles even when the reference is 2 frames but only contains about 82k logical gates.The results show that this hardware architecture can efficiently improve the processing speed and meets the requirements of 1080p@30fps AVS-P2 video real-time decoding.