A GALS-Based Quad-Core Interconnection and Task Scheduling Mechanism Research

This paper presents a Quad-core digital signal processor design based on GALS (Global Asynchronous Local Synchronous) and interconnected with two DMA channels.GALS based design guarantees each core could work in different frequency domains according to the task request, thus the chip's total power consumption can be reduced and eliminate the difficulties on the constrains of the global clocks.Intercommunication with DMA channels between each core achieves high efficiency of data transmission with less processor load.A task scheduling mechanism based on the data flow is proposed to manage the tasks on each core which improves the efficiency of the processor and a MP3 decoder program is implemented on this processor to elaborate the task partition and schedule of the tasks and show the performance of the processor.