The Design of Memory Streaming Access System of Reconfigurable Cipher Stream Processor

This paper mainly points at the existence of "memory bottleneck" between the cipher processor and external memory. From this aspect, reconfigurable memory streaming access system is designed for the processor, it uses pipelined parallel transmission of data channels and takes memory streaming access scheduling strategy which depends on bursting transmission mode. It optimizes the transmission efficiency of external memory accessing and improves performance of the cipher processor. Experimental results show that, comparing with common access modes of cipher processors, memory access efficiency of the design can be increased nearly 5.9 times.