Instruction Reuse Optimization Based on Post-dominance

We propose a method for instruction reuse based on post-dominance. In compiler there’s a pass analyze post-dominator of conditional branches and control-independent instructions in post-dominator, result will be encoded as a "hint" instruction before corresponding branch. Modified rename stage in CPU salvages instruction results selectively according to "hint" instruction, which will reduce penalty of branch misprediction. Our evaluation showed that a short hardware table could provide performance improvements of up to 1.97%.