Structure Design and FPGA Implementation of a Variable Dimension FFT Hardware Accelerator

The large number of Fast Fourier Transform (FFT) has high requirements on the processor's computing and memory bandwidth. It is usually the bottlenecks of DSP applications with strong real-time demand. It is of great practical value to study the FFT accelerator with high speed, low resource consumption and easy hardware.In this paper, a variable dimension FFT hardware accelerator is designed. By using the data form of body-surface-line, the calculation is carried out from two levels of surface and line. It adopts surface partitioning¹and multiple parallel architecture to improve the parallelism of FFT. Furthermore by using Ping-Pong operation, pre-read and flexible address adjustment to conceal data transmitting time. In this paper, the FFT accelerator consists of 32 parallel computing units to carry out 2ⁿ(n is from range of 5 to 16) single-precision floating-point 1-D FFT and 2ⁿ (n is from range of 5 to 8) single-precision floating-point 2-D/3-D FFT. What is more, it is important that the structure has strong expansibility which can achieve FFT of the sequence of m×n×p. As a result the design's maximal frequency is up to 184.88 MHz. It has been successfully applied on the Xilinx Virtex6 FPGA chip.