Design and Implementation of New Structure 8B/10B Encoder

In consideration of the demand of high-speed data communication, a new structure high speed 8B/10B encoder is designed and implemented.The proposed encoder architecture is realized based on pipeline and parallel processing.After being synthesized using 65 nm process, the proposed encoder achieves the operating frequency 1 GHz and occupies the chip area of 321 μm².The results show that it can reduce the area of the circuit and improve the efficiency of encode.