A Statistical-Based Digital Background Calibration for Pipelined ADC

Pipelined ADCs with high resolution need calibration technique to increase their conversion precision. The statistical-based digital background calibration technique presented here calculates the output error via statistic analysis, and then the error is subtracted from the ADC output. With this calibration architecture used in a 14-bit pipelined ADC, the simulation results show that after calibration the SNR is 76.9 dB, SFDR is 73.9 dB, and the EN0B is improved from 9 bit to 12.5 bit.