FPGA-based Design of Accelerator for Convolution Layer of Convolutional Neural Network

With the development of hardware, deep learning has been a hot area again, in which Convolutional Neural Network (CNN) shows excellent performance in several aspects. Convolution layer is the most important part of CNN, and has lots of multiplications and additions. For this feature, a FPGA-based accelerator with pipelineis designed for convolution layer. The designed circuit can compute one result in a single clock cycle. Under the same framework and dataset, FPGA has nearly 7x and 5x computational efficiency of CPU and GPU, and has only 28.87% power consumption of GPU.