A Macroblock-parallel and Resuable VLSI Architecture of H .264 Intra Decoder

This paper presents a VLSI architecture design of macroblock-parallel intraframe decoder to avoid the data conflicts,providing guarantee for decdoding correctness.The memory reuse,calculation unit reuse and macroblock-parallel intra prediction module is designed which can improve the decoding speed and increase the utilization of resources at the same time.The functional testing and DC analysis has demonstrated the proposed macroblock-parallel VLSI architecture of intra decoder.It achieves a decoding speed at 113 cycles/MB.