A 12-Bit 60 MHz Pipeline ADC Based on 40 nm CMOS Process

A 12-bit 60 MHz high-performance pipeline ADC is designed in this paper, which consists of sample/hold circuit, 1.5-bit/stage conversion circuit applied from 1^st to 10^th and a 2-bit flash ADC of the last stage. In this design a gate-bootstrapping switch was used to reduce nonlinear, an operational amplifier with a gain-boosting folded cascade input stage and a class AB output stage was used, dynamic latch comparator was used too, meanwhile, optimizing the sampling capacitor, the gain and bandwidth of the operational amplifier in the circuit stage by stage. In a SMIC 40 nm CMOS process, when the input signal frequency was 1.875 MHz and the sampling frequency was 60 MHz, the SNDR was 68.7 dB, the SFDR was 74.6 dB, the ENOB was 11.12 bits, the core area of chip was 0.95 mm², the total dissipation current was 56 mA under the 1.1 V supply voltage.