Background Timing-Skew Calibration Algorithm for the TIADC Based on Zero-Crossing Detection

A background calibration technique, which is based on zero-crossing detection method, for clock mismatch in Time-Interleaved Analog-to-Digital Converter (TIADC) is proposed. The error is achieved by comparing the amount of zero-crossing in channels to control the delay for the purpose of timing skew calibration. The algorithm is verified by an 8 bits 5-channels TI ADC MATLAB model. The simulation result shows that the ENOB rises from 5.16 bits to 7.88 bits, and the SNR rises from 32.8 dB to 49.4 dB at the f_in/f_s=0.461, which means the correctness and effectiveness of the algorithm is validated. The presented calibration in this paper has no restriction on the input signal frequency, and can be extended to arbitrary number of channels.