Design of a Full Load Stability High-PSRR Low Dropout Regulator

An improved power supply ripple rejection (PSRR) low drop-out (LDO) voltage regulator circuit is proposed. The LDO improves the ability of power supply ripple rejection ratio by improving power supply rejection ratio of the bandgap reference. This approach is tested in TSMC 0.18 μm COMS process. The results show that the maximum load current is 80 mA, and the open-loop phase margin is not less than 64° at a load current from 0 to 80 mA which proves the high stability of LDO. In addition, the circuit achieves a transient response with 15 mV voltage variation and 0.5 μs settling time for an 80 mA load step. The PSRR at 10 kHz is -60.82 dB and 100kHz is 57.66 dB.