BIST Circuit Design for Network-on-chip Memory

Network-on-chip(Network-on-chip,NoC) as a solution to solve the problems of System-on-chip,the test technology based on network-on-chip has caused more and more attention.Test technology of NoC is one of the important parts.In this method,we research on fault model of SRAM memory and establish the functional model of NoC's communication architecture, design the BIST circuit reusing network-on-chip as TAM (Test Access Mechanism)to test SRAM memory based on March C + algorithm.This method was designed by verilog language, and implement the test in NoC system platform based on FPGA.Experiment results show that this method has a high fault coverage with the small increase in area overhead.