The Design of Ultra-Low Power Wake-Up Receivers Applied to ETCS

Based on the standard of DSRC, paper introduce the application of wake-up receivers in ETCS. By using the proposed design scheme, wake-up receiver has been achieved, which have low power and high sensitivity. The circuit module, such as bias circuit, amplifier circuit, comparator, current reference source and drive, are implemented based on 0.13 μm CMOS process. The op amp has lower power consumption and high gain by using optimizing structure of circuit. A comparator with hysteresis is used to reduce the interference of noise and comparator offset on the comparator output. Simulation result shows that the wake-up receiver can work in the 2 V~3.3 V power supply voltage and -40~80℃ temperature. The detection sensitivity of the baseband is -68.3 dBm and the DC current is 6.97 μA typically.