A Low Power 14-Bit 10 MS/s Pipelined A/D Converter

A low power 14 bit 10MS/s pipelined analog-to-digital converter (ADC) using 0.6 μm BiCMOS process is presented.Some methods to realize low power pipelined ADC will be proposed.These methods include removing the active S/H, sharing the op-amp between adjacent multi-bit-per-stages, scaling down and designing high performance low power operation amplifier technique.To reduce aperture error without the active S/H, a simple RC time constant matching method is used.Simulation results show that a SNDR of 80.17 dB, a SFDR of 87.94 dB, and an ENOB of 13.02 bits are achieved.The ADC consumes 55 mW at 5 V supply.