Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR

In this paper, a second-order CDR based on phase interpolator is designed for 10Gbase-KR. Through linear modeling and analysis, it makes a compromise between jitter tolerance, lock-in time and jitter peak value, and the appropriate gain coefficient is selected. The circuit is designed by SMIC 40 nm CMOS process, in which the ratio and integral coefficient of the second-order filter can be adjusted to track the deviation of 1 000 ppm, and the worst case of recovery clock jitter is 24 ps.