Design and Implementation of High Performance Asynchronous FIFO

This paper presents a high performance FIFO design that interfaces subsystems on a chip working at different speeds. The communication protocol and the architecture of FIFO are proposed at first. Aim at improving its operation speed, the design of storage array, read/write control logic and full/empty status logic are described specifically. Compared with the existing FIFO block, the design’s performance improvement ratio is more than 30 percent.