Method and Implementation of Instruction Set Extension for AES on MIPS Processor

Because of the limit of the data bus of the MIPS Processor,the instruction extension for Advanced Encryption Standard(AES) algorithms on MIPS Processor can′t well implement the parallel processing of AES. Taking advantage of the result register of multiplier on MIPS Processor,it can implement 64bit encryption/ decryption to increase its parallel processing capacity,this method can′t raise the number of the registers on MIPS. And the pipeline processing of the critical byte substitution phase and mix-column phase of the AES algorithms could use the idle cycle of the MIPS′s pipeline cycle,it decrease the critical path of the extension module.It compares the performance of different implementation and the results show that this method reduces the critical path to let the processor run at a high frequency,but it decreases a large area of the chip,also it has the advantage of the flexible programming.