Design and implementation of convolution neural network accelerator based on FPGA

FPGAs are widely used in the implementation of hardware accelerators for convolutional neural networks. This paper designs a FPGA-based CNN acceleration structure. It mainly utilizes the inherent parallelism in CNN to reduce the bandwidth and resource usage required by real-time embedded applications, and implements it on the ZC706 development board with limited resources. The results show that the FPGA operates at a frequency of 0.54 GOP/s and consumes very little power at 150 MHz.