Design and implementation of high performance FFT processor based on conflict-free access rules

The high-performance Fast Fourier Transform (FFT) processor has a wide range of application scenarios in real-time signal processingsystems such as radar and communication. In this paper, a high performance FFT processor is designed by optimizing the conflict-free access rules and combining the radix-2 and radix-8 DIT-FFT. The processor employs a Memory-Based architecture, including a butterfly operator unit, a memory unit, and a control unit. The calculation speed and hardware efficiency are improvedImprove calculation speed and hardware efficiency by optimizing Conflict-Free access rules and twiddle factor generation schemes. The proposed processor is implemented on SMIC 40 nm CMOS technology. Simulation results show that the processor can work at over 500 MHz, the core area is1.76×0.85mm², and the SNR is over136dB or more. Under the 32K-point FFT calculation task, the calculation speed is about 4 times higher than that of the same type of FFT processor.