Design and Application of High Speed Dual-Field Multiplier

Dual-Field multiplier is the important component of Dual-Field Montgomery multiplier and has important meaning for elliptic curve cryptography. Considering that the critical path of Dual-Field multiplier depends on the GF(p) field, Partial product generating circuit and Wallace compressor circuit was optimized based on traditional radix-4 Booth encoder multiplier(GF(p)) to support both GF(p) and GF(2 m) field. The designed Dual-Field multiplier implemented on FPGA shows that the area is decreased by 16.9% compare to the separating implement. The delay is increased by 1.188 ns than the traditional field GF(p). The designed Dual-Field multiplier is applied to Montgomery multiplier. The time for 256 bit Montgomery multiplier of our design is reduced by 7.35% than paper proposed.