Design of a Wide-Range Programmable Frequency Synthesizer

A wide-range programmable frequency synthesizer is presented in this work.This frequency synthesizer uses self-biased DLL and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems.The programmable frequency-multiplied output can be quickly switched between x1, x2, x4 and x8 without affecting the lock state of the DLL.The Voltage Initial Selector is used to decrease the locking time.The proposed DLL frequency synthesizer, which has been realized in a CMOS 130-nm, can generate clock signal ranging from 14 to 700 MHz at 1.8 V supply.The total power dissipation is only 28.44 mW and the cycle-to-cycle jitter is about 9.8-ps at 400 MHz.