Design of novel CMOS majority logic gate

One-Step Majority Logic Decodable (OS-MLD) can be used to protect memory from soft errors caused by single-particle flips in where Majority Logic Gate (MLG) plays an important role in the decoders. However, the existing MLG circuits require more hardware overhead. This paper proposes a new type of MLG circuit which consists of a PMOS pull-up network, an NMOS pull-down network, and an inverter. Simulation verification with Cadence software shows that the proposed circuits not only correctly perform majority logic, but also feature lower overhead in terms of power consumption, delay, and area, compared with the existing MLG circuits. At the same time, the designed MLG is applied to OS-MLD, and the results show that the proposed MLG is effective for this coding application.