An effective converter to translate XDL netlist description file into directed hyper-graph

The XDL netlist description file of the FPGA is not only used to parse for the extraction of the instance and net inside FPGA design, but also used to translate into the general abstract signal propagation model of FPGA netlist. In this paper, the directed hyper-graph is used to describe the FPGA internal signal forward topology, whose vertex can be considered as the in-use pin of instance and directed hyper-edge can be represented as the net connection or the instance function between the in-use pins of instance. Furthermore, this paper not only presents the workflow of the converter to translate XDL netlist description file into directed hyper-graph, but also gives the EBNF expression of the XDL compiler and the translate algorithm of directed hyper-graph. Finally, this paper implements the converter in Windows OS and JAVA based on the source code of RapidSmith software. The experiment of the test bench of Xilinx′s Virtex-4 shows that the converter could translate XDL netlist description file into directed hyper-graph. The correctness and effectiveness of the converter based on the translate algorithm of directed hyper-graph is also proved by the experiment.