A Hardware Framework of SAT Solver

HE An-ping, MAO Le-le, CHEN Zhi-xue, WU Jin-zhao. A Hardware Framework of SAT Solver[J]. Microelectronics & Computer, 2016, 33(9): 124-127.

Citation:

HE An-ping, MAO Le-le, CHEN Zhi-xue, WU Jin-zhao. A Hardware Framework of SAT Solver[J]. Microelectronics & Computer, 2016, 33(9): 124-127.

Citation:

HE An-ping, MAO Le-le, CHEN Zhi-xue, WU Jin-zhao. A Hardware Framework of SAT Solver[J]. Microelectronics & Computer, 2016, 33(9): 124-127.

Abstract

In this paper, we customized the FPGA chip to fit the SAT problem, e.g., translating and compiling the large scale system, and then seccessfully solved the problem by FPGA autonomously.

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