Parallel Acceleration Design of Convolutional Neural Network Based on FPGA

Sccording to the characteristics of convolutional neural network, this paper proposes a pipeline parallel acceleration scheme of FPGA. Convolution module circuit, activation module circuit and down-sampling module circuit are designed to construct the FPGA basic unit of convolution neural network operation. With the same network structure and processing data, FPGAs with 50 MHz frequency are 8x and nearly 5x computational efficiency of the CPU and the GPU, while power consuming only 27.8% of the GPU.