Design and Verification of High-performance LDPC Encoder IP Core

A semi-parallel LDPC encoder architecture was proposed for Error correction coding used in a solid state hard drive (SSD) which is the representative of large capacity and high throughput memory based on the mathematical characteristics of excellent LDPC codes. Then SIMD instruction scheduling control flow approach was applied to achieve the RU coding algorithm; LDPC encoder whose parameters such as bit rate and code length were dynamically configurable was designed. The correctness of the encoder was verified through Xilinx FPGA platform and co-simulation of Matlab and ModelSim; Tests showed that configuration time was less than 7 us and the encoder achieved a throughput of 4.82 Gb/s using fewer resources compared with other encoders when the operating frequency is 100 MHZ.