ZHANG Xi, WANG Xin, TONG Wei, HUO Zong-liang. A low-cost PMU circuit for 3D NAND Flash memory testing[J]. Microelectronics & Computer, 2020, 37(5): 1-5.
Citation: ZHANG Xi, WANG Xin, TONG Wei, HUO Zong-liang. A low-cost PMU circuit for 3D NAND Flash memory testing[J]. Microelectronics & Computer, 2020, 37(5): 1-5.

A low-cost PMU circuit for 3D NAND Flash memory testing

  • In order to improve the cost of the chip caused by the high price of the 3D NAND tester, a new FPGA-based low-cost PMU (precision measurement unit) circuit for DC parameter testing of 3D NAND memory chips is proposed. The flexible programmable feature of the FPGA is used to implement the PMU circuit by controlling the discrete components of the ADC, DAC and relays so that the PMU circuit can test DC parameters with FVMI (Force Voltage Measure Current) and FIMV (Force Current Measure Voltage) function. The PMU circuit has been applied to the YMTC self-developed 3D NAND Flash test platform, which can accurately measure the DC parameters of the 3D NAND, and the cost of the test machine is only 0.175% of the cost of the large ATE machine, thus alleviating the problem of excessive test cost of the chip.
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