Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration

This paper designs and realizes a delay hidden mechanism for FPGA runtime reconfiguration. Through the pages management of FPGA, the cache architecture design and caching policy research, the mechanism can hid the configuration delay of BIT file, improve the overall efficiency in the multiple tasks scheduling. It gives FPGA the same user mode with GPU, provides the idea of using FPGA in computing technology more widely.