A Receiver Circuit Design for High Speed On-Chip Global Interconnect

In on-chip communication,with the development of SOC and NOC and the increment number of cores embedded in a single system,the global interconnects are becoming a speed and power bottleneck.Low swing global interconnect,which has emerged as a solution to higher data rate and lower power consumption application,is mainly consist of the transmitter and receiver.In this paper,a half-rate clock receiver circuit with DFE,which is used in low swing global interconnect,is designed based on TSMC 90nm CMOS technology.The receiver consists of a new improved sense amplifier structure and an analog DFE used to eliminate the ISI on the output signals.The half-rate clock strategy is used to double the bit-rate on the receiver.The proposed receiver achieves a better average power consumption comparing with the related structure,while the delay and unit energy are nearly the same.