The Design of MOS Current Mode Logic Frequency Divider

The MCML (MOS current mode logic) latch is designed with optimized parameters.Its power consumptionand delay is analyzed and simulated.Based on this latches, the 1:2 and the 1:4 frequency divider is designed, respectively.The maximum operating frequency of the 1:2 frequency divider is 7.7 GHz.The 1:4 frequency divider has be realized by two 1:2 frequency dividers in cascade.Without buffers, the 1:4 frequency divider reduce the first stage output node capa-citance, and reduce the area of the chips.Circuits were simulated in the SMIC 0.13μm CMOS technology.